Wireless telecommunication technology, such as HSDPA, begins to use hybrid automatic repeat request (HARQ) technology. When the received information after decoding has an error (for example, the error in cyclic redundancy check (CRC) check) due to existence of interference and fading of wireless channels, the receiving end may ask the sending end to resend the information to the receiving end, and the resent information may be the same with or different from the original information. The receiving end can combine the information received last time and the information that is currently resent for analysis, so as to obtain correct information. Since the original information needs to be retained to be combined with the resent information of the next time, this information needs to be stored by the memory.
The receiving end needs to use a memory to store all the error information packets, which are placed in a HARQ soft bit buffer or a HARQ memory. For a HSDPA with a low data velocity, such a memory used to store the HARQ information is small and may be implemented by a static random access memory (SRAM). When high speed data and various HARQ processes exist, sometimes such a memory is considerably big. For LTE technology, data velocity is very high, for example Category 3, whose data velocity is 50 Mbps for upstream and 100 Mbps for downstream, and whose total soft bit number for downstream is 1237248 (as shown in Table 1). If 8 bits are used to represent one soft bit, a 1.2 Mbyte memory is needed to support Category 3. Such a big memory (SRAM) used on the chip will increase the chip area and thus cause lack of competitiveness.
TABLE 1downlink physical layer parameter values set by UE CategoryMaximumMaximumnumber ofnumberbits ofMaximumof DL-SCHa DL-SCHnumber oftransporttransportsupportedblock bitsblocklayersreceivedreceivedTotal numberfor spatialUEwithin awithin aof soft channelmultiplexing inCategoryTTITTIbitsDLCategory 110296102962503681Category 2510245102412372482Category 31020487537612372482Category 41507527537618270722Category 530275215137636672004
To reduce the chip area, the HARQ memory can be implemented by an off-chip double data rate SDRAM (DDR)/synchronous dynamic random access memory (SDRAM). However, the implementation of the off-chip SDRAM takes up large bandwidth of DDR/SDRAM, and furthermore, the large quantity of accesses of the off-chip memory will directly increase the power consumption of the chip. Therefore, the existing HARQ memory needs to be improved urgently.